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ASIC-System On Chip (SoC)-VLSI Design
http://asic-soc.blogspot.com/
Its all about VLSI, ASIC, SoC: CMOS Design, Layout, Digital Design, Verilog HDL,Synthesis,Static Timing Analysis (STA),Design For Test(DFT),Physical Design,Floorplanning,Power Planning,Clock Tree Synthesis (CTS),Placement,Routing,Physical Verification,Formal Verification....!
Recent Posts
CoreConnect Bus and AMBA Bus Specification Resources
"CoreConnect" and "AMBA" are the two prominent bus architectures used in System on Chip designs. These architectures define technology independent standard bus protocol methodologies for easy integration of IPs within a System on Chip design. "CoreCO...
System on Chip article links
Recently i came across some System on Chip (SoC) design related articles from design-reuse website. Enjoy good reading:Getting the most from multiprocessor SoC designSoC integration complexities riseChallenges in developing a reusable IP core USB OTG...
Clock Definitions
lock Definitions: Rising and falling edge of the clock For a +ve edge triggered design +ve (or rising) edge is called ‘leading edge’ whereas –ve (or falling) edge is called ‘trailing edge’. For a -ve edge triggered desi...
Transition Delay and Propagation Delay
Transition Delay Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum value. This is known as “rise time”. Transition Delay or Slew Similarly “fall t...
Net Delay or Interconnect Delay or Wire Delay or Extrinsic Delay or Flight Time
Net Delay or Interconnect Delay or Wire Delay or Extrinsic DelaNet delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. It is due to the finite resistance and capa...
Delays in ASIC Design
Delays We encounter several types of delays in ASIC design. They are as follows: Gate delay or Intrinsic delay Net delay or Interconnect delay or Wire delay or Extrinsic delay or Flight time Transition or Slew Propagation delay...

