Recent Posts Tagged With 'cadence'

• ITC: Test is getting harder, conferences getting smaller…

  Posted on Sunday November 8th, 2009 at 15:04 in Feature, blog posts, itc, mentor, cadence, synopsys, siliconaid, xjtag, itc 2009

  Happy Sunday!  Test week is over, participants are back to their normal lives, perhaps off to another conference.  Last time I blogged, it was Monday, after the first panel and 40th year reception.  I’m going to try to blog a few notes throu...

• DFT-in-the-news: 4/05/2009

  Posted on Sunday April 5th, 2009 at 12:21 in industry news, mentor, cadence, jtag, synopsys, asset intertech, xjtag, logicvision

  Wow, it's been so long since I done "in-the-news", this might get to be a long post... the DFT world moves on whether I have time to document it or not! The following are a selection of press releases from the first quarter of this year; I'll follow...

• DFT-in-the-News, 11/02/2008

  Posted on Monday November 3rd, 2008 at 00:01 in industry news, mentor, cadence, jtag, teradyne, asset intertech, corelis, intellitech, itc 2008, ieee 1149.1, teseda

  Intellitech unveils low-power Bluetooth based IEEE 1149.1/JTAG Pod with non-volatile test and failure memory Santa Clara, California – International Test Conference - October 30th, 2008 – Intellitech Corporation, www.intellitech.com, the leader ...

• ITC Day 2 - All Gassed Up About Compression

  Posted on Friday October 31st, 2008 at 09:00 in gas, blog posts, mentor, cadence, synopsys, test compression, verigy, itc 2008, logicvision

  Test Compression makes test vectors for efficient - I wish there was such a thing for schedules... ITC Day 2 for me seemed like a lot of running around, trying to find people, trying to avoid people [joking! really...], answering e-mails, phone calls...

• Fight the Power! Turning Down the Heat on Scan

  Posted on Wednesday October 8th, 2008 at 01:41 in Feature, cadence, synopsys, atpg, at-speed test, power-aware test

  I suppose this little late-summer/early-autumn heat wave in SoCal makes one want to talk about heat. Makes sense to me - but what's the excuse for these folks, presumably from the notably cooler Northern California? In the past few days, two diff...

• DFT-related DAC news

  Posted on Wednesday May 28th, 2008 at 00:37 in industry, DAC, mentor, cadence, bist, dft, scan atpg, oci, test compression, genesys, logiccvision, synoopsys

  This week, I’ll try to pass along Design-for-Test related DAC news as it comes along… First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Tech...

• Deep Chip survey results and DFT - believe John or Gary?

  Posted on Monday March 31st, 2008 at 08:57 in industry, mentor, gary smith, cadence, eda, bist, dft, synopsys, scan atpg, test compression, esnug, john cooley

  Last week, John Cooley published the results of his 2008 DeepChip Synopsys Survey, and of course I went straight to item #6, entitled “Synopsys DFT Compiler/TetraMAX vs. Mentor DFT Advisor/FastScan“. There are some surprises and head sc...