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Recent Posts Tagged With 'interview'
Latch based Interview Question
Latch-based designs are sometimes used for high-speed digital circuits. One possible configuration places combinational logic between a pair of latches with opposite polarities (one latch is active hi...
NVIDIA Interview Question
Two stages are added to the pipeline discussed in the earlier post to form the circuit shown below.1.2. Stage A decides to send the input either to stages B-C or to stage D.3. 35% of data from stage A...
NVIDIA Interview Question
Your task is to develop a method to reduce the power consumption of the 2-stage image processing pipeline shown below (clock inputs are not shown for simplicity).NOTES:1. 2. The capacitance of an in...
NVIDIA Interview Question
Circuit below, which implements operation C, has been designed such that it has two modules i and j, with the delays shown in the given figure below. The latency for circuit b is 2 and the delay throu...
NVIDIA Interview Questions
You are designing a circuit that implements two operations A and B as shown below.NOTES:1. At any point in time the circuit is doing either A or B.2. Delays through modules of each operation are given...
NVIDIA Interview Questions
State whether each of the following statements is True or False . Justify your answers.RTL simulation is faster than delta-cycle simulation but can not be used in all situations.When doing RTL design...
Pipelining Interview Question
Pipelining is particular form of retiming where the goal is to increase the throughput (number of results per second) of a circuit. Consider the circuit diagram below; the solid rectangles represent...
Logic Design Interview Question
In thinking about the propagation delay of a ripple-carry adder, we see that the higher-order bits are "waiting" for their carry-ins to propagate up from the lower-order bits. Suppose we split off t...
CMOS Interview Question
Occasionally you will come across a CMOS circuit where the complementary nature of the n-channel pull-downs and p-channel pull-ups are not obvious, as in the circuit shown below:Construct a table th...
STA Interview Question
Suppose we are building circuits using only the following three components: inverter: tcd = 0.5ns, tpd = 1.0ns, tr = tf = 0.7ns 2-input NAND: tcd = 0.5ns, tpd = 2.0ns, tr = tf = 1.2ns 2-input NOR: ...
STA Interview Question
Suppose that each component in the circuit below has a propagation delay (tpd) of 10ns, a contamination delay (tcd) of 1ns, and negligable rise and fall times. Suppose initially that all four inputs...
Interview Question
Your company, EarGuard Inc., is working on the q-pod, a new music player. The chief verification engineer has just reported that a bug has been discovered in the qDub module of the q-pod. The verifica...
Interview Question
You are on the committee to define a uniquely Indian Hardware Description Language: IndieHDL — a cool language from a hot country. One proposal is to restrict the language so that IndieHDL supports ...
Interview Question - Intel, Folsom
Your next co-op job is with the Independent Eagle-Eyed Elective, a consulting firm that performs code reviews for other companies. Your first task is to review the VHDL code for a new traffic-light co...
Interview Question
Some software programming languages allow compilers to perform "short cut" or "short circuit" optimizations on AND and OR operations. In a short-cut AND or OR, the second argument is not evaluated if ...
Inverter madness - Interview Question
The following graph plots the voltage transfer characteristic for a device with one input and one output. Can this device be used as a combinational device in a logic family with 0.75V noise margins?Y...
Digital Abstraction - Interview Question
The behavior of a 1-input, 1-output device is measured by hooking a voltage source to its input and measuring the voltage at the output for several different input voltages: We're interested in wheth...
VHDL Interview Question(s)
What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect?What is the advantage of RTL ...
Funny twist with compression and performance - Interview Question
The organization Scholastic Lecture Expert Productivity Testers (SLEPT), has defined a standardized algorithm to compress digital-video lectures by removing irrelevant material. The company you work f...
The Good, the Bad, and the Unsynthesizable - Interview Questions
For each of the code fragments, answer whether the code is legal VHDL.If the code is legal VHDL, answer whether it is synthesizable.If the code is synthesizable:answer whether it represents good codin...
Texas Instruments, Bangalore - Interview Questions - Freshers
For the following question, you only need to give the relevant VHDL code fragment (i.e. process that drives the flop). You may assume that any signals you need or want to use are defined appropriately...
Interview Question - Bangalore
Assume a clock-gating scheme for turning off the clock in certain situations:60% of the time, the main circuit has valid datathe clock gating circuitry is 80% effectivethe clock gating circuitry has a...
Qualcomm Interview Questions - Bangalore
The average performance of products in your market segment triples every 36 months. Your design engineers have proposed an optimization that will increase performance by 12%. The optimization will pos...
Broadcom Bangalore - Interview Questions
The new vice president of your company has set up a contest for ideas to reduce leakage power in the next generation of chips that the company fabricates. The prize for the person who submits the sugg...
Interview Questions - Computer Architecture
Some more pointers..Boolean logic MinimizationState machine designSynchronous circuit timing, races, testabilityPipelines and hazardsProcessor block diagrams, Cache architecture Microarchitecture tech...
Interview Questions - VLSI
This is a general checklist for freshers to take on the job hunting adventure...CMOS gates, complex gates, Latch and FF designRegions of operation of a MOSFET, IV characteristics in different regions,...
Interview Question - Scan Test
A 1.2GHz chip has scan chains of length 30,000 bits, 20,000 bits, 24,000 bits, 25,000 bits, and two of 12,000 bits. 500,000 test vectors are used for each scan chain. The tests are run at 50% of full ...
Interview Question - Effects on power
The VLSI gurus at your company have come up with a way to decrease the average rise and fall time (0-to-1 and 1-to-0 transitions) for signals. The current value is 1ns. With their fabrication tweaks, ...
Interview Question - Timing Analysis
If you were to compare a typical digital circuit from 5 years ago with a typical digital circuit today, would you find that the percentage of the total clock period consumed by capacative load has inc...
Interview Question - Low power design
The new vice president of your company has set up a contest for ideas to reduce leakage power in the next generation of chips that the company fabricates. The prize for the person who submits the sugg...