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Recent Posts Tagged With 'vhdl'
HDL Coding Guidelines - Part 7
HintsAvoid more package references than neededKeep all objects and subprograms in the nearest possible scopeKeep local objects invisible outside a packageTransfer stable component declarations into co...
HDL Coding Guidelines - Part 6
To Avoid common WarningsStore each VHDL unit into a separate file except package header and bodySignal assignments for renaming purposes should be avoidedThe names of clocks and resets should be uniqu...
HDL Coding Guidelines - Part 5
Critical Policies to Keep note!Balance clock to delta accuracyPull-ups and pull-downs have to be modeled on chip levelCommunication between modules using text-IO is forbiddenNo characters with a lower...
HDL Coding Guidelines - Part 4
To Avoid common ErrorsA configuration declaration is needed for each architecture in the designDesign-internal references must use library workUse selected names in binding indications and ’use’ c...
HDL Coding Guidelines - Part 3
PortabilityLanguage for modeling should be VHDL-87VHDL-93 keywords should not be usedVerilog keywords should not be usedSDF keywords should not be usedIKOS keywords should not be usedAllowable replac...
HDL Coding Guidelines - Part 2
When Compiling (VHDL):A configuration declaration is needed for each architecture in the designDesign-internal references must use library workUse selected names in binding indications and ’use’ c...
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It has a major impact on logic synthesis, routing results, timing robustness, verif...
VHDL Interview Question(s)
What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect?What is the advantage of RTL ...
The Good, the Bad, and the Unsynthesizable - Interview Questions
For each of the code fragments, answer whether the code is legal VHDL.If the code is legal VHDL, answer whether it is synthesizable.If the code is synthesizable:answer whether it represents good codin...