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Posted on Thursday January 22nd, 2009 at 23:01 in hold, setup
savita: hi u know what i was reading that chat session u have Who says chatting is bad habit! Here is a chat session between two friends about deadly dangerous setup and hold!! Don’t think that the person who is asking these qu...
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Posted on Friday August 22nd, 2008 at 00:54 in synthesis, static timing analysis (sta), timing analysis
Recently i had a good chat session with my new friend bgs and i feel it is good idea to share the same..... it may clear or evoke some more doubts you have in your mind. I have given chat session as it is to maintain the originality. Please bear wit...
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Posted on Sunday July 6th, 2008 at 23:54 in vlsi, synthesis, asic, static timing analysis (sta), timing analysis, physical design
Senior Physical design engineer position, Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. The questions are also related to St...
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Posted on Wednesday June 18th, 2008 at 01:14 in digital design, basic gates using mux
Related faqAND gate using MUXOR gate using MUXNAND gate using MUXNOR gate using MUXXOR gate using MUX ...
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Posted on Wednesday June 18th, 2008 at 01:12 in digital design, basic gates using mux
Related faqAND gate using MUXOR gate using MUXNAND gate using MUXNOR gate using MUXXNOR using MUX ...
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Posted on Wednesday June 18th, 2008 at 01:11 in digital design, basic gates using mux
Related faqAND gate using MUXOR gate using MUXNAND gate using MUXXOR gate using MUXXNOR using MUX ...
nice posts man
Check this: http://only-vlsi.blogspot.com/
Posted: May 30th, 2009 | Report This Comment